Adjustment circuit for voltage division

ABSTRACT

An adjustable circuit for voltage division comprises a serial resistor Rn(n=1, 2 . . . n) symmetrically mapped, connected in series, and paired in parallel with a switch Sn or Sn&#39; apiece, wherein the switches Sn and Sn&#39; are oppositely operated, namely, when the former is turned &#34;ON/OFF&#34;, the latter is turned &#34;OFF/ON&#34; to thereby hold the current unchanged to obtain desired output voltage(s) by proper control of the switches and accordingly a valid portion of voltage-dividing resistor DELTAR&#39;.

FIELD OF THE INVENTION

This invention relates generally to an adjustment circuit for voltage division, particularly to an adjustment circuit applicable to a voltage divider with constant current for adjusting divided resistance or resolution in a respectively larger scope while keeping the total resistance unchanged.

BACKGROUND OF THE INVENTION

A voltage divider is implemented frequently in circuits to divide voltage for output of an expected voltage value. For convenience, an adjustable voltage divider is preferred for trimming in the case an offset to some extent is found in the value of the expected output voltage.

In a conventional adjustment method shown in FIG. 1, a serial resistor R_(n)(n=0, 1, 2 . . . N) is connected in series and paired in parallel with a corresponding switch S₀, S₁ . . . S_(N) apiece to form an adjustable voltage-dividing resistor ΔR, and an output voltage V_(o) equal to V_(dd)(R_(out)+ΔR′)/(R_(in)+R_(out)+ΔR) is obtained (where ΔR′ is a valid portion of voltage-dividing resistor equal to 0 or ΔR). Examples are presented as in the following:

If the switches S_(A) and S_(B) are turned “ON” while the rest switches don't care, then

V _(o) =V _(dd) ×R _(out)÷(R _(in) +R _(out)).

If the switch S_(A) is turned “ON” only while the rest switches are turned “OFF”; then

V _(o) =V _(dd)×(R_(out) +R ₀ +R ₁ +R ₂ +R ₃ + . . . +R _(n))/(R _(in) +R _(out) +R ₀ +R ₁ +R ₂ +R ₃ + . . . +R _(n)).

If the switches S_(A) and S₀ are turned “ON” while the rest switches are turned “OFF”; then

V _(o) =V _(dd)×(R _(out) +R ₁ +R ₂ +R ₃ + . . . +R _(n))/(R _(in) +R _(out) +R ₁ +R ₂ +R ₃ + . . . +R _(n)).

If the switches S_(A), S₀, and S₁ are turned “ON” while the rest switches are turned “OFF”; then

V _(o) =V _(dd)×(R _(out) +R ₂ +R ₃ +R ₄ + . . . +R _(n))/(R _(in) +R _(out) +R ₂ +R ₃ +R ₄ + . . . +R _(n)).

If the switch S_(B) is turned “ON” only while the rest switches are turned “OFF”; then

V _(o) =V _(dd) ×R _(out)/(R _(in) +R _(out) +R ₀ +R ₁ +R ₂ +R ₃ + . . . +R _(n)).

If the switch S_(B) and S₀ are turned “ON” while the rest switches are turned “OFF”; then

V _(o) =V _(dd) ×R _(out)/(R _(in) +R _(out) +R ₁ +R ₂ +R ₃ + . . . +R _(n)).

If the switches S_(B), S₀, and S₁ are turned “ON” while the rest switches are turned “OFF”; then

V _(o) =V _(dd) ×R _(out)/(R _(in) +R _(out) +R ₂ +R ₃ +R ₄ + . . . +R _(n)).

The switches are properly controlled such that the adjustable voltage-dividing resistor ΔR can be adjusted proportionally to obtain a desired output voltage Vo. Now, suppose R_(n)=2^(n)R, then ΔR=(S₀2⁰+S₁2¹+ . . . +S_(n)2^(n))R, where S_(n) is 0 or 1. When S_(n) in FIG. 1 is turned “ON”, S_(n) is 0, otherwise, S_(n) is 1 and R=1 accordingly, so that ΔR is adjustable proportionally in the range of (S₀2⁰+S₁2¹+ . . . +S_(n)2^(n)) as mentioned. However, such a voltage divider structure is inapplicable to a voltage division system that requires a constant current because of its variable resultant resistance and current, and is defective in adjusting or providing multiple outputs V_(o).

For improvement, an amended design has been proposed later on as shown in FIG. 2, wherein an adjustable voltage-dividing resistor ΔR comprises a serial resistor R_(n) including resistor R₀, R₁, R₂, . . . R_(n) connected in series and corresponding switch S₀, S₁, . . . S_(n) in parallel to obtain an output voltage V₀₁=V_(dd)×(R_(out 1)+R_(out 2)+ΔR₁′+ΔR₂)/(R_(in)+R_(out 1)+R_(out 2)+ΔR₁+ΔR₂), where ΔR₁′ is a variable and another output voltage V₀₂=V_(dd)×(R_(out 2)+ΔR₂′)/(R_(in)+R_(out 1)+R_(out 2)+ΔR₁+ΔR₂), where ΔR₂′ is a variable.

Taking V₀₁ for example, adjustment may be made as the following:

If the switch S₀ is turned “ON” while the rest switches are turned “OFF”, then

V ₀₁ =V _(dd)×(R _(out 1) +R _(out 2) +R ₀ +R ₁ + . . . +R _(n) +ΔR ₂)/(R _(in) +R _(out 1) +R _(out 2) +R ₀ +R ₁ + . . . +R _(n) +ΔR ₂).

If the switch S₁ is turned “ON” while the rest switches are turned “OFF”, then

V ₀₁ =V _(dd)×(R _(out 1) +R _(out 2) +R ₁ + . . . +R _(n) +ΔR ₂)/(R _(in) +R _(out 1) +R _(out 2) +R ₀ +R ₁ + . . . +R _(n) +ΔR ₂).

The variable valid voltage-dividing resistor ΔR₁′ can be adjusted to obtain a desired or multiple outputs V_(o) by controlling the switches properly in a voltage division system operated under a constant current, whereas, the voltage-dividing resistor ΔR is not suited to be adjusted proportionally in the range of (S₀2⁰+S₁2¹+ . . . +S_(n)2^(n)).

SUMMARY OF THE INVENTION

The primary object of this invention is to provide an adjustment circuit for voltage division, which is implemented in an adjustable voltage-dividing resistor ΔR comprising a symmetrically mapped serial resistor(R_(n)) and paired switches(S_(n)), wherein a valid portion of voltage-dividing resistor ΔR′ can be adjusted proportionally in the range of (S₀R₀+S₁R₁+ . . . +S_(n)R_(n)).

For more detailed information regarding advantages or features of this invention, at least an example of preferred embodiment will be elucidated below with reference to the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The related drawings in connection with the detailed description of this invention, which is to be made later, are described briefly as follows, in which:

FIG. 1 shows a conventional adjustment circuit for voltage division;

FIG. 2 shows another conventional adjustment circuit for voltage division;

FIG. 3 shows an adjustment circuit of this invention for voltage division;

FIG. 4 shows a preferred embodiment of the adjustment circuit for multiple output voltage division; and

FIG. 5 shows an example of the adjustment circuit for voltage division.

DETAILED DESCRIPTION OF THE INVENTION

In an adjustment circuit for voltage division of this invention shown in FIG. 3, a serial resistor R_(n)(n=1, 2 . . . n) is mapped symmetrically, connected in series, and paired in parallel with a switch Sn or Sn′ apiece to hold valid an equation V_(o)=V_(dd)(R_(out)+ΔR′)/(R_(in)+R_(out)+ΔR) (where ΔR=R₀+R₁+ . . . +R_(n)′ and ΔR′ is a valid portion of voltage-dividing resistor variable depending on control of the S_(n) and S_(n)′ serial switches; V_(o) is the output voltage). The switch S_(n) and S_(n)′ are operative oppositely, namely, when the switch S_(n) is turned “ON/OFF”, the switch S_(n)′ is turned “OFF/ON” on the contrary. A voltage division architecture of this kind is applicable to a voltage division system with constant current and expandable for control of multiple outputs (shown in FIG. 4). If R_(n)=2^(n)R, then the valid portion of voltage-dividing resistor ΔR′ can be adjusted proportionally in the range of (S₀2⁰+S₁2¹+. . . +S_(n)2^(n)). Several examples are presented below with reference to the adjustment circuit for voltage division shown in FIG. 5.

Suppose R_(in)=20, R_(out)=20, ΔR=1+2+4=7, thus:

if the switches S₁, S₂, and S₄ are turned “OFF” (namely, the switches S₁′, S₂′, and S₄′ are turned “ON”), then

V _(o)=20/(20+20+7);

if the switch S₁, S₂, and S₄′ are turned “OFF” (namely, the switches S₁′, S₂′, and S₄ are turned “ON”), then

V _(o)=(20+4)/(20+20+7);

if the switch S₁, S₂′, and S₄′ are turned “OFF” (namely, the switches S₁′, S₂, and S₄ are turned “ON”), then

V _(o)=(20+2+4)/(20+20+7);

if the switches S₁′, S₂′, and S₄′ are turned OFF (namely, the switches S₁, S₂, and S₄ are turned ON), then

V _(o)=(20+1+2+4)(20+20+7); and

if the switches S₁′, S₂, and S₄′ are turned OFF (namely, the switches S₁, S₂′, and S₄ are turned ON), then

V _(o)=(20+1+4)/(20+20+7).

Hence, this invention can be utilized to adjust ΔR′, the valid portion of voltage-dividing resistor ΔR, proportionally in a range including the combinations from 0 to 7, and expansively, in the range of (S₀2⁰+S₁2¹+ . . . +S_(n)2^(n)) under a constant current without changing the total resistance.

Besides, the valid portion of voltage-dividing resistance ΔR′ can be adjusted bi-directionally (±ΔR′) to provide a wider flexible range in circuit design.

For example,

if the switches S₁, S₂, and S₄′ are turned “OFF” (namely, the switches S₁′, S₂′, and S₄ are turned “ON”), then

V _(o)=24/(20+20+7);

now the conditions are changed that the switches S₁, S₂, and S₄ are turned “OFF” (namely, the switches S₁′, S₂′, and S₄′ are turned “ON”), then

V _(o)=(24−4)/(20+20+7).

Therefore, the adjustment circuit for voltage division of this invention can be bi-directionally adjusted (±ΔR′) so as to flexibly enlarge the adjustable range.

In the above described, at least one preferred embodiment has been described in detail with reference to the drawings annexed, and it is apparent that numerous variations or modifications may be made without departing from the true spirit and scope thereof, as set forth in the claims below. 

What is claimed is:
 1. An adjustment circuit for voltage division having an adjustable voltage-dividing resistor ΔR composed of a serial resistor R_(n)(n=0, 1, 2 . . . n) mapped symmetrically, connected in series, and paired in parallel with a switch S_(n) or S_(n)′ apiece, wherein the switches S_(n) and S_(n)′ are oppositely operated, namely, if S_(n) is turned “ON/OFF”, S_(n)′ is turned “OFF/ON” to thereby adjust a valid portion of the voltage-dividing resistor ΔR proportionally for obtaining a desired output voltage by controlling the switches S_(n) and S_(n)′(n=0, 1, 2 . . . n).
 2. The adjustment circuit according to claim 1, wherein the symmetrical serial resistor R_(n) equals 2^(n)R.
 3. The adjustment circuit according to claim 1, wherein the initial state of the adjustment circuit is set that the switch S₁, S₂ . . . S_(n)′ are turned “OFF” while the switches S₁′, S₂′ . . . S_(n) are turned “ON”.
 4. The adjustment circuit according to claim 2, wherein the initial state of the adjustment circuit is set that the switches S₁, S₂ . . . S_(n)′ are turned “OFF” while the switches S₁′, S₂′ . . . S_(n) are turned “ON”.
 5. An adjustment circuit for voltage division, comprising: an input resistor R_(in); an output resistor R_(out); and an adjustable voltage-dividing resistor ΔR further comprising a symmetrically mapped serial resistor R_(n)(n=1, 2 . . . n), connected in series, and paired in parallel with a switch S_(n) or S_(n)′ apiece, wherein the switch S_(n) is operative oppositely against the switch S_(n)′, namely, when the switch S_(n) is turned “ON”, the switch S_(n)′ is turned “OFF” and vice versa, so that the output voltage V_(o)=V_(dd)(R_(out)+ΔR′)/(R_(in)+R_(out)+ΔR) is always held valid, where ΔR=(R_(0+R) ₁+R₂+ . . . +R_(n)) and ΔR′ is a variable depending on control of the switches and applicable in the range of (S₀R₀+S₁R₁+ . . . +S_(n)R_(n)).
 6. The adjustment circuit according to claim 5, wherein the symmetrical serial resistor R_(n) equals 2^(n)R.
 7. The adjustment circuit according to claim 5, wherein the input resistor R_(in) is further connected in series with the adjustable voltage-dividing resistor ΔR and the output resistor R_(out) for providing multiple outputs.
 8. The adjustment circuit according to claim 5, wherein the initial state of the adjustment circuit is set that the switches S₁, S₂, . . . , and S_(n)′ are turned “OFF” while the switches S₁, S₂′, . . . and S_(n)′ are turned “ON”.
 9. The adjustment circuit according to claim 6, wherein the initial state of the adjustment circuit is set that the switches S₁, S₂, . . . , and S_(n)′ are turned “OFF” while the switches S₁′, S₂′, . . . , and S_(n)′ are turned “ON”. 